1. Field of the Invention
The present invention relates to chemical-mechanical polishing and, more particularly, to an apparatus for polishing and cleaning a semiconductor wafer.
2. Description of the Prior Art
Silicon wafers used for very large scale integration (VLSI) circuits are ideally flat. However, after many process steps, such as growth or deposition of various insulating and conductive layers, a nonplanar structure is usually formed. For example, the gate oxide of a metal oxide semiconductor (MOS) transistor is only 100-250 angstroms thick, whereas the field oxide may be 10,000 angstroms thick. The nonplanarity primarily results in two problems. The first problem is the difficulty of maintaining step coverage without breaks in the continuity of fine lines. The second problem is the inability to lithographically transfer fine-line patterns to the wafer.
More specifically, lithography techniques have steadily shifted toward the use of shorter wavelengths, such as the deep ultraviolet (DUV), in order to reduce minimum feature size. Unfortunately, decreasing the wavelength results in reducing the depth of focus (DOF). The depth of focus is an important parameter because the surface of a microcircuit has a nonplanar topographical surface. Therefore, the number of photolithography steps required to cover the microcircuit is increased, thereby increasing the time required to fabricate the microcircuit.
Techniques for planarization have been proposed to address the disadvantages associated with nonplanar surfaces. Chemical-mechanical polishing (CMP) is one of many conventional planarizing techniques used in fabricating VLSI circuits. Chemical-mechanical polishing is used as an attempt to attain a planar surface over the entire semiconductor substrate. FIG. 1A shows a cross-sectional view of a conventional CMP apparatus 10, which includes a rotating table 12 having a polishing pad 14 disposed thereon, and a rotating holder 16 that holds a wafer 18. A predetermined pressure is exerted on the wafer 18 by the polishing pad 14. As shown in FIG. 1B, a magnified cross-sectional view, an appropriate slurry 19 is applied between the wafer 18 and the polishing pad 14.
As the size of wafers has increased, a different kind of CMP apparatus 20 has been proposed to improve polishing efficiency. This CMP apparatus 20 includes a rotating table 26 that has a wafer 28 disposed thereon, and a holder 22, which is rotating or stationary, for holding a polishing pad 24. A simplified top view of this CMP apparatus 20 is shown in FIG. 2B, illustrating only the wafer 28 and the polishing pad 24.
During the polishing process, the CMP apparatus 10 (FIG. 2A) and the CMP apparatus 20 (FIG. 2A) will generate, either chemically or mechanically, unwanted particles. Such particles represent impurity concentrations that, however slight, can degrade the performance of VLSI circuits. Therefore, cleaning is essential to remove the unwanted particles and to achieve high production yield and device reliability.
In the conventional CMP process, the polished or unfinished wafers are removed from the CMP apparatus to a cleaner where some particle removal method, such as scrubbing and rinsing, is applied to remove the unwanted particles. To adequately complete the CMP process, a wafer must typically be subjected to the cleaning steps involving the CMP apparatus and the cleaner numerous times. Repeated transferring of the wafers back and forth between the CMP apparatus and the cleaner undesirably reduces production efficiency. Moreover, the transferring of the wafers further contaminates the clean environment necessary during VLSI fabrication.